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74ABT373 Octal Transparent Latch with 3-STATE Outputs
January 1993 Revised November 1999
74ABT373 Octal Transparent Latch with 3-STATE Outputs
General Description
The ABT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state.
Features
s 3-STATE outputs for bus interfacing s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching, noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down s Nondestructive hot insertion capability
Ordering Code:
Order Number 74ABT373CSC 74ABT373CSJ 74ABT373CMSA 74ABT373CMTC 74ABT373CPC Package Number M20B M20D MSA20 MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names D0-D7 LE OE O0-O7 Description Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) 3-STATE Latch Outputs
(c) 1999 Fairchild Semiconductor Corporation
DS011547
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74ABT373
Functional Description
The ABT373 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.
Truth Table
Inputs LE H H L X OE L L L H Dn H L X X Output On H L On (no change) Z
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance State
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ABT373
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current: (Across Comm Operating Range) Over Voltage Latchup (I/O) twice the rated IOL (mA) OE Pin Other Pins -150 mA -500 mA 10V -0.5V to +5.5V -0.5V to VCC -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (V/t) Data Input Enable Input 50 mV/ns 20 mV/ns -40C to +85C +4.5V to +5.5
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test 4.75 2.5 2.0 0.55 1 1 7 -1 -1 Min 2.0 0.8 -1.2 Typ Max Units V V V V V A A A V A A mA A A A mA A mA mA mA mA/ 0.12 MHz Max Min Min Min Max Max Max 0.0 VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA IOH = -3 mA IOH = -32 mA IOL = 64 mA VIN = 2.7V (Note 4) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 4) VIN = 0.0V IID = 1.9 A All Other Pins Grounded Output Leakage Current Output Leakage Current Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current -100 10 -10 -275 50 100 50 30 50 Outputs Enabled Outputs 3-STATE Outputs 3-STATE ICCD Dynamic ICC (Note 4)
Note 3: For 8 bits toggling, ICCD < 0.8 mA/MHz. Note 4: Guaranteed, but not tested.
0 - 5.5V VOUT = 2.7V; OE = 2.0V 0 - 5.5V VOUT = 0.5V; OE = 2.0V Max Max 0.0 Max Max Max VOUT = 0.0V VOUT = VCC VOUT = 5.5V; All Others GND All Outputs HIGH All Outputs LOW OE = VCC All Others at VCC or GND VI = VCC - 2.1V Enable Input VI = VCC - 2.1V Data Input VI = VCC - 2.1V All Others at VCC or GND Outputs Open, LE = VCC OE = GND, (Note 3) One Bit Toggling, 50% Duty Cycle
Additional ICC/Input
2.5 2.5 2.5
No Load
Max
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74ABT373
DC Electrical Characteristics
(SOIC Package) Symbol VOLP VOLV VOHV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage -1.2 2.5 2.0 Min Typ 0.4 -0.8 3.0 1.7 0.9 0.6 Max 0.8 Units V V V V V VCC 5.0 5.0 5.0 5.0 5.0 Conditions CL = 50 pF, RL = 500 TA = 25C (Note 5) TA = 25C (Note 5) TA = 25C (Note 6) TA = 25C (Note 7) TA = 25C (Note 7)
Note 5: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested. Note 6: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 7: Max number of data inputs (n) switching. n - 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Packages) TA = +25C Symbol Parameter Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time 1.9 1.9 2.0 2.0 1.5 1.5 2.0 2.0 VCC = +5.0V CL = 50 pF Typ 2.7 2.8 3.1 3.0 3.1 3.1 3.6 3.4 Max 4.5 4.5 5.0 5.0 5.3 5.3 5.4 5.4 TA = -55C to +125C VCC = 4.5V to 5.5V CL = 50 pF Min 1.0 1.0 1.0 1.5 1.0 1.5 1.7 1.0 Max 6.8 7.0 7.7 7.7 6.7 7.2 8.0 7.0 TA = -40C to +85C VCC = 4.5V to 5.5V CL = 50 pF Min 1.9 1.9 2.0 2.0 1.5 1.5 2.0 2.0 Max 4.5 4.5 5.0 5.0 5.3 5.3 5.4 5.4 ns ns ns ns Units
AC Operating Requirements
(SOIC and SSOP Packages) TA = +25C Symbol Parameter Min fTOGGLE tS(H) tS(L) tH(H) tH(L) tW(H) Max Toggle Frequency Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE Pulse Width, LE HIGH 1.5 1.5 1.0 1.0 3.0 VCC = +5.0V CL = 50 pF Typ 100 Max TA = -55C to +125C VCC = 4.5V to 5.5V CL = 50 pF Min 100 2.5 2.5 2.5 2.5 3.3 1.5 1.5 1.0 1.0 3.0 Max TA = -40C to +85C VCC = 4.5V to 5.5V CL = 50 pF Min Max MHz ns ns ns Units
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74ABT373
Extended AC Electrical Characteristics
(SOIC Package) TA = -40C to +85C VCC = 4.5V to 5.5V Symbol Parameter CL = 50 pF 8 Outputs Switching (Note 8) Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPZL Output Disable Time Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time 1.5 1.5 1.5 1.5 1.5 1.5 1.0 1.0 Max 5.2 5.2 5.5 5.5 6.2 6.2 5.5 5.5 Min 2.0 2.0 2.0 2.0 2.0 2.0 (Note 11) (Note 9) Max 6.8 6.8 7.5 7.5 8.0 8.0 2.0 2.0 2.0 2.0 2.0 2.0 TA = -40C to +85C VCC = 4.5V to 5.5V CL = 250 pF TA = -40C to +85C VCC = 4.5V to 5.5V CL = 250 pF 8 Outputs Switching (Note 10) Min Max 9.0 9.0 9.5 9.5 10.5 10.5 (Note 11) ns ns ns ns Units
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 11: The 3-STATE delay times are dominated by the RC network (500, 250 pF) on the output and has been excluded from the datasheet.
Skew
(SOIC Package) TA = -40C to +85C VCC = 4.5V-5.5V Symbol Parameter CL = 50 pF 8 Outputs Switching (Note 12) Max tOSHL (Note 14) tOSLH (Note 14) tPS (Note 16) tOST (Note 14) tPV (Note 15) Pin to Pin Skew, HL Transitions Pin to Pin Skew, LH Transitions Duty Cycle, LH-HL Skew Pin to Pin Skew, LH/HL Transitions Device to Device Skew, LH/HL Transitions 1.0 1.0 1.4 1.5 2.0 TA = -40C to +85C VCC = 4.5V-5.5V CL = 250 pF 8 Outputs Switching (Note 13) Max 1.5 1.5 3.5 3.9 4.0 ns ns ns ns ns Units
Note 12: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 13: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-to-LOW (tOST). This specification is guaranteed but not tested. Note 15: Propagation delay variation is for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Note 16: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Capacitance
Symbol CIN COUT (Note 17) Parameter Input Capacitance Output Capacitance Typ 5 9 Units pF pF VCC = 0V VCC = 5.0V Conditions (TA = 25C)
Note 17: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74ABT373
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load Amplitude 3.0V Rep. Rate 1 MHz tw 500 ns
FIGURE 2. Test Input Signal Levels tr 2.5 ns tf 2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times
FIGURE 5. Propagation Delay, Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms
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74ABT373
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body Package Number M20B
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74ABT373
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74ABT373
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20
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74ABT373
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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74ABT373 Octal Transparent Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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